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-- Company: 
-- Engineer: 
-- 
-- Create Date: 2022/08/03 17:31:50
-- Design Name: 
-- Module Name: QOXY - ART
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY QOXY IS
  PORT (
    CLOCK : IN STD_LOGIC;
    KZD : IN STD_LOGIC;
    YZZ : IN STD_LOGIC;
    DATA : IN STD_LOGIC_VECTOR (0 TO 3);
    XYJG : OUT BOOLEAN);
END QOXY;

ARCHITECTURE ART OF QOXY IS
  SIGNAL S1 : STD_LOGIC;
BEGIN
  PROCESS IS
    VARIABLE V1 : STD_LOGIC;
  BEGIN
    WAIT UNTIL CLOCK'EVENT AND CLOCK = '1';
    IF KZD = '1' THEN
      FIRST : S1 <= YZZ;
    END IF;
    V1 := '0';
    FOR I IN DATA'RANGE LOOP
      V1 := V1 XOR DATA(I);
    END LOOP;
    SECOND : XYJG <= (V1 = S1);
  END PROCESS;
END ART;